1. Field of the Invention
The present invention relates to a voltage translator to be used for a semiconductor integrated circuit, and more particularly to a voltage translator for wordline driving of a flash EEPROM.
2. Description of Related Art
In a semiconductor integrated circuit, a plurality of voltages may be used internally. Particularly in a flash EEPROM, different voltages are required depending on the mode of memory operation in addition to the normal logical control voltage Vdd and earth potential. Typically the voltage to be applied to a wordline is about 5V for a read operation, about 12V for a write operation, and about xe2x88x929V for an erase operation. These operating voltages are not absolute values but are values to be changed as semiconductor manufacturing processing advances.
A circuit having a function to supply voltage other than the logical control voltage Vdd and earth potential to a wordline is called a xe2x80x9cvoltage translatorxe2x80x9d. A circuit disclosed in Japanese Unexamined Patent Publication No. H10-149693 is an example thereof. FIG. 4 shows an outline of the circuit of the voltage translator stated in the above mentioned publication. This voltage translator 400 has a configuration where the wordline WL is connected to about a 5.5V operating voltage source VX via a first PMOS switch transistor P1 on the one hand, and is connected to the voltage source VXGND, which is the earth potential, via the first NMOS switch transistor N1.
This voltage translator 400 is further comprised of a second PMOS feedback transistor P2 which is directly driven depending on the voltage level of the wordline WL, and a second NMOS feedback transistor N2-r which is directly driven depending on the voltage level of the wordline WL. The voltage translator 400 also includes an inverter INV1-r which inverts and outputs signals from the decoder shown as the NOR circuit NOR1, and the output terminal of the inverter INV1-r is connected to the control electrode of the first NMOS switch transistor N1. According to the above mentioned publication, in this configuration, the. 5.5V operating potential VX of the wordline and the OV earth potential are switched at high-speed using the ON and OFF of the second NMOS feedback transistor N2-r.
However, the operating voltage of the flash EEPROM could be a value other than 5.5V and 0V depending on the operation mode. In the conventional voltage translator 400 shown in FIG. 4, it is possible to select one wordline from the many wordlines (not illustrated) of the voltage translator connected to the voltage source VXGND so as to execute a read operation and a write operation.
However, an erase operation cannot be executed with one selected wordline. This is because when a xe2x88x929V voltage is applied to the voltage source VXGND, the first NMOS switch transistor turns ON since a voltage more than the threshold voltage of the first NMOS switch transistor is applied between the first main electrode and the control electrode of the first NMOS switch transistor, even if the control electrode is 0V (xe2x80x9cLxe2x80x9d level). As a result, the voltage of all the wordlines connected to the voltage source VXGND become xe2x88x929V. Therefore the voltage translator 400 can be applied only to a batch erasing type flash EEPROM.
If voltage in the xe2x80x9cLxe2x80x9d level is input to both input terminals IN1 and IN2 of the decoder NOR1 when the potential of the wordline is xe2x88x929V, the control potential of the connection point 6, that is, the first PMOS switch transistor P1, becomes 0V, where this transistor is in ON status.
In other words, both the first PMOS switch transistor P1 and the first NMOS switch transistor N1 become ON status, where a through current flows continuously from the voltage source VX to the voltage source VXGND.
As a consequence, a voltage translator which can supply voltage less than the earth potential, only to a selected wordline, has been desired.
It is an object of the present invention to provide a voltage translator which can supply a positive operating voltage to a selected wordline, and also which can supply an operating voltage less than the earth potential, which is different from the above operating voltage, depending on the decoder signal.
It is another object of the present invention to provide a voltage translator where the speed of switching the wordline voltage to the earth voltage is increased by disposing an NMOS transistor having a feedback function in the circuit configuration.
It is still another purpose of the present invention to provide a voltage translator which switching speed is faster.
It is still another purpose of the present invention to provide a voltage translator where the configuration can be compact with a small number of transistors.
For this, the voltage translator of the present invention is connected to the first operating voltage source and the second operating voltage source. The voltage translator supplies a positive first operating voltage from the first operating voltage source, or supplies a second operating voltage lower than the earth potential from the second operating voltage source to a wordline depending on the output signal of the decoder, and has the following features. In other words, the voltage translator of this invention is comprised of the first and second NMOS transistors and the first and second PMOS transistors.
The first PMOS transistor has a first main electrode connected to the first operating voltage source, and a second main electrode connected to the wordline.
The first NMOS transistor has a first main electrode connected to the second operating voltage source, and a second main electrode connected to the wordline.
The second PMOS transistor has a first main electrode connected to the first operating voltage source, a second main electrode connected to a control electrode of the first PMOS transistor, and a control electrode connected to the wordline.
The second NMOS transistor has a first main electrode connected to the second operating voltage source, a second main electrode connected to a control electrode of the first NMOS transistor, and a control electrode connected to the wordline.
The second PMOS transistor functions as a feedback transistor in the voltage translator, and controls the first PMOS transistor P1. The second NMOS transistor also functions as a feedback transistor in the voltage translator, and controls the first NMOS transistor N2.
According to such a configuration, a positive first operation voltage can be supplied, and a second operating voltage less than the earth potential can be supplied to a selected wordline, depending on the output signal of the decoder.